The present invention relates to semiconductor devices having multiple tiers of bond wires and, more particularly, to a semiconductor device with a brace for preventing wires in separate tiers from contacting each other.
Many semiconductor devices use bond wires for connecting bonding pads of an integrated circuit die to leads of a lead frame or pads of a substrate. As integrated circuits have become smaller and include more functionality, multiple tiers of bond wires are needed to connect the die bond pads with leads/substrate pads. Referring to FIG. 1, a packaged semiconductor device 10 is shown. The device 10 includes an integrated circuit (IC) die 12 attached to a flag 14 of a lead frame with a die attach material such as an adhesive 16. The IC die 12 is electrically connected to leads of the lead frame with bond wires, with the leads providing for connection to external circuitry and devices. In this case, the device 10 includes a set of inner leads 18 and a set of outer leads 20. A first set of bond wires 22 connect bond pads of the die 12 to the inner leads 18 and a second set of bond wires 24 connect bond pads of the die 12 to the outer leads 20. The second set of wires 24 may be longer than the first set wires 22 because they extend from in-board bond pads to outer leads 20 whereas the wires of the first set 22 extend from bond pads near the edge of the die 12 to inner leads 18. Thus, the bonding wires of the second set 24 may have a substantial length.
Such devices with multiple tiers of bond wires often encounter wire short problems due to wire sagging. For example, since the wires of the second set 24 are long, they can have a tendency to sag, as shown with wire 26. Optimized looping profiles do not ensure 100% elimination of wire sagging. The incidence of shorting can be more problematic if there is only one row of leads (i.e., only outer leads 20) to which both sets of wires 22, 24 extend.
In view of the foregoing, it would be desirable to have a method of preventing wires from multiple tiers or of differing loop heights from shorting.